1. Field of the Invention
The invention relatives to a method for forming a junction region of a semiconductor device, more particularly to the method for forming a junction region of a PMOS semiconductor device.
2. Description of the Prior Art
As semiconductor devices, such as complementary metal-oxide-semiconductor devices, become highly integrated, the area occupied by the devices shrinks, as well as the design rule. With advances in semiconductor technology, the dimensions of the integrated circuit (IC) devices have shrunk to the deep sub-micron region, some problems are incurred due to the process of scaling down.
With the progress of semiconductor elements, the manufacturing of semiconductor elements is more and more precise and therefore, the depth distribution of impurity atoms is more and more precise. In generally, an ion implanting method is used to precisely control the depth and concentration distributions of the impurity atoms. In the process of ion implanting, the impurity atoms with a form of charged ions are accelerated to have energy and then they can collide the silicon wafer directly to enter into a proper position in the crystal lattices. Therefore, the depth distribution of the ions can be controlled by the energy of the ion, while the dose of the impurities can be controlled by the implanting time and current of the ion beam.
In the prior art, the charged ions as an ion beam with certain energy is implanted into a silicon wafer by using an ion implanter. Then, an annealing process required for activating impurities and recovering damage, thereby causing a redistribution of the implanted ions and the occurrence of a transient enhance diffusion (TED) phenomenon. Consequently, it is difficult to form ultra shallow junctions by traditional ion-implantation. Moreover, when the line width of the devices is required to be reduced to be below 90 nm, and area of each section, including source and drain, in the metal oxide semiconductor (MOS) must also be reduced, and thus the diffusing depth of the junction must be controlled severely for reducing the short channel effect and the punch-through effect.
As device scaling for the 90 nm technology node and beyond, ultra shallow and low sheet resistance source/drain extensions (SDE) are required to suppress the short channel effect and to obtain high current drivability. Recent study has been shown towards carbon implantation as an approach for fabricating ultra shallow junctions by low energy implantation, carbon atom act to sink silicon interstitials, thereby reducing enhanced dopant diffusion. However, introduction of carbon by ion implantation can lead to higher leakage current in p-n junctions and lower throughput in production. Accordingly, it is one of considerable issues on the application of carbon implantation.